Performance evaluation of full adder
نویسندگان
چکیده
منابع مشابه
Performance evaluation of full adder
This paper presents different techniques of one bit Full adder. In every technique the main requirements are power consumption, speed and power delay product. The proposed FIN-FET technique gives the bette.r power consumption, speed and power delay product than other techniques. The proposed Fin-FET technique is compared with some of the popular adders based on the power consumption, speed and ...
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در این پایان نامه پارامترهای مهم در مدارات دیجیتال توضیح داده شده و چند سلول جمع کننده متداول مورد بررسی قرار گرفته است. ایده های مختلفی که در پیاده سازی مدارات جمع کننده وجود داشته، شبیه سازی شده است. در پیاده سازی مدار سلول جمع کننده، در بعضی از مقالات طبقات ورودی و در بعضی دیگر طبقات خروجی متفاوت است. در مقالات متفاوت از منطق های cmos مکمل، نسبتی، ترانزیستور عبوری مکمل، گیت های انتقال، تابع ...
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متن کاملAnalysis and Performance Evaluation of 1-bit Full Adder Using Different Topologies
An adder is a digital circuit that performs addition of numbers and it plays an important role in today’s digital world. In processors and other kinds of computing devices, Adders are used in the arithmetic logic units. They are also utilized in other parts of the processors for calculating addresses, table indices, increment and decrement operations and other similar operations because it is t...
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ژورنال
عنوان ژورنال: IOSR Journal of Electronics and Communication Engineering
سال: 2017
ISSN: 2278-8735,2278-2834
DOI: 10.9790/2834-1202023437